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ltc2053/ltc2053-sync 2053syncfc typical a pplica t ion fea t ures descrip t ion precision, rail-to-rail, zero-drift, resistor-programmable instrumentation amplifier the ltc ? 2053 is a high precision instrumentation ampli - fier. the cmrr is typically 116db with a single or dual 5v supply and is independent of gain. the input offset voltage is guaranteed below 10v with a temperature drift of less than 50nv/c. the ltc2053 is easy to use; the gain is adjustable with two external resistors, like a traditional op amp. the ltc2053 uses charge balanced sampled data tech - niques to convert a differential input voltage into a single ended signal that is in turn amplified by a zero-drift op - erational amplifier. the differential inputs operate from rail-to-rail and the single-ended output swings from rail-to-rail. the ltc2053 can be used in single-supply applications, as low as 2.7v. it can also be used with dual 5.5v supplies. the ltc2053 requires no external clock, while the ltc2053-sync has a clk pin to synchronize to an external clock. the ltc2053 is available in an ms8 surface mount pack - age. for space limited applications, the ltc2053 is avail - able in a 3mm 3mm 0.8mm dual fine pitch leadless package (dfn). typical input referred offset vs input common mode voltage (v s = 3v) a pplica t ions n 116db cmrr independent of gain n maximum offset voltage: 10v n maximum offset voltage drift: 50nv/c n rail-to-rail input n rail-to-rail output n 2-resistor programmable gain n supply operation: 2.7v to 5.5v n typical noise: 2.5v p-p (0.01hz to 10hz) n typical supply current: 750a n ltc2053-sync allows synchronization to external clock n available in ms8 and 3mm 3mm 0.8mm dfn packages n thermocouple amplifiers n electronic scales n medical instrumentation n strain gauge amplifiers n high resolution data acquisition l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. differential bridge amplifier + ? ltc2053 2 3 7 8 0.1 f 3v r < 10k 1, 4 5 6 r2 10k 2053 ta01 out 0.1 f r1 10 gain = 1+ r2 r1 input common mode voltage (v) 0 input offset voltage (v) 15 10 5 0 ?5 ?10 ?15 0.5 1.0 1.5 2.0 2053 ta01b 2.5 3.0 v s = 3v v ref = 0v t a = 25c g = 1000 g = 100 g = 10 g = 1
ltc2053/ltc2053-sync 2053syncfc a bsolu t e maxi m u m r a t ings total supply voltage (v + to v C ) ................................. 11v input current ........................................................ 10ma | v C in C v ref | ........................................................... 5.5v | v + in C v ref | ............................................................ 5.5v output short-circuit duration .......................... indefinite operating temperature range ltc2053c, ltc2053c-sync ................... 0c to 70c ltc2053i, ltc2053i-sync .................. C40c to 85c ltc2053h .......................................... C40c to 125c (note 1) top view 9 dd package 8-lead (3mm s 3mm) plastic dfn 5 6 7 8 4 3 2 1 en ?in +in v ? v + out rg ref t jmax = 125c, ja = 160c/w , underside metal internally connected to v C (pcb connection optional) en /clk ? ?in +in v ? 1 2 3 4 8 7 6 5 v + out rg ref top view ms8 package 8-lead plastic msop t jmax = 150c, ja = 200c/w ?pin 1 is en on ltc2053 , clk on ltc2053-sync p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc2053cdd#pbf ltc2053cdd#trpbf laeq 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc2053idd#pbf ltc2053idd#trpbf laeq 8-lead (3mm 3mm) plastic dfn C40c to 85c ltc2053hdd#pbf ltc2053hdd#trpbf laeq 8-lead (3mm 3mm) plastic dfn C40c to 125c ltc2053cms8#pbf ltc2053cms8#trpbf ltvt 8-lead plastic msop 0c to 70c ltc2053ims8#pbf ltc2053ims8#trpbf ltjy 8-lead plastic msop C40c to 85c ltc2053hms8#pbf ltc2053hms8#trpbf ltafb 8-lead plastic msop C40c to 125c ltc2053cms8-sync#pbf ltc2053cms8-sync#trpbf ltbnp 8-lead plastic msop 0c to 70c ltc2053ims8-sync#pbf ltc2053ims8-sync#trpbf ltbnp 8-lead plastic msop C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ storage temperature range ms8 package ..................................... C65c to 150c dd package ....................................... C65c to 125c lead temperature (soldering, 10 sec) ................... 300c
ltc2053/ltc2053-sync 2053syncfc e lec t rical c harac t eris t ics parameter conditions min typ max units gain error a v = 1 l 0.001 0.01 % gain nonlinearity a v = 1, ltc2053 a v = 1, ltc2053-sync l l 3 3 12 15 ppm ppm input offset voltage (note 2) v cm = 200mv C5 10 v average input offset drift (note 2) t a = C40c to 85c t a = 85c to 125c l l C1 50 C2.5 nv/c v/c average input bias current (note 3) v cm = 1.2v l 4 10 na average input offset current (note 3) v cm = 1.2v l 1 3 na input noise voltage dc to 10hz 2.5 v p-p common mode rejection ratio (notes 4, 5) a v = 1, v cm = 0v to 3v, ltc2053c, ltc2053c-sync a v = 1, v cm = 0.1v to 2.9v, ltc2053i, ltc2053i-sync a v = 1, v cm = 0v to 3v, ltc2053i, ltc2053i-sync a v = 1, v cm = 0.1v to 2.9v, ltc2053h a v = 1, v cm = 0v to 3v, ltc2053h l l l l l 100 100 95 100 85 113 113 113 db db db db db power supply rejection ratio (note 6) v s = 2.7v to 6v l 110 116 db output voltage swing high r l = 2k to v C r l = 10k to v C l l 2.85 2.95 2.94 2.98 v v output voltage swing low l 20 mv supply current no load l 0.75 1 ma supply current, shutdown v en 2.5v, ltc2053 only 10 a en /clk pin input low voltage, v il 0.5 v en /clk pin input high voltage, v ih 2.5 v en /clk pin input current v en /clk = v C C0.5 C10 a internal op amp gain bandwidth 200 khz slew rate 0.2 v/s internal sampling frequency 3 khz the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 3v, v C = 0v, ref = 200mv. output voltage swing is referenced to v C . all other specifications reference the out pin to the ref pin. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 5v, v C = 0v, ref = 200mv. output voltage swing is referenced to v C . all other specifications reference the out pin to the ref pin. parameter conditions min typ max units gain error a v = 1 l 0.001 0.01 % gain nonlinearity a v = 1 l 3 10 ppm input offset voltage (note 2) v cm = 200mv C5 10 v average input offset drift (note 2) t a = C40c to 85c t a = 85c to 125c l l C1 50 C2.5 nv/c v/c average input bias current (note 3) v cm = 1.2v l 4 10 na average input offset current (note 3) v cm = 1.2v l 1 3 na common mode rejection ratio (notes 4, 5) a v = 1, v cm = 0v to 5v, ltc2053c a v = 1, v cm = 0v to 5v, ltc2053c-sync a v = 1, v cm = 0.1v to 4.9v, ltc2053i a v = 1, v cm = 0.1v to 4.9v, ltc2053i-sync a v = 1, v cm = 0v to 5v, ltc2053i, ltc2053i-sync a v = 1, v cm = 0.1v to 4.9v, ltc2053h a v = 1, v cm = 0v to 5v, ltc2053h l l l l l l l 105 100 105 100 95 100 85 116 116 116 116 116 db db db db db db db power supply rejection ratio (note 6) v s = 2.7v to 6v l 110 116 db
ltc2053/ltc2053-sync 2053syncfc e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 5v, v C = 0v, ref = 200mv. output voltage swing is referenced to v C . all other specifications reference the out pin to the ref pin. parameter conditions min typ max units output voltage swing high r l = 2k to v C r l = 10k to v C l l 4.85 4.95 4.94 4.98 v v output voltage swing low l 20 mv supply current no load l 0.85 1.1 ma supply current, shutdown v en 4.5v, ltc2053 only 10 a en /clk pin input low voltage, v il 0.5 v en /clk pin input high voltage, v ih 4.5 v en /clk pin input current v en /clk = v C C1 C10 a internal op amp gain bandwidth 200 khz slew rate 0.2 v/s internal sampling frequency 3 khz parameter conditions min typ max units gain error a v = 1 l 0.001 0.01 % gain nonlinearity a v = 1 l 3 10 ppm input offset voltage (note 2) v cm = 0v 10 20 v average input offset drift (note 2) t a = C40c to 85c t a = 85c to 125c l l C1 50 C2.5 nv/c v/c average input bias current (note 3) v cm = 1v l 4 10 na average input offset current (note 3) v cm = 1v l 1 3 na common mode rejection ratio (notes 4, 5) a v = 1, v cm = C5v to 5v, ltc2053c a v = 1, v cm = C5v to 5v, ltc2053c-sync a v = 1, v cm = C4.9v to 4.9v, ltc2053i a v = 1, v cm = C4.9v to 4.9v, ltc2053i-sync a v = 1, v cm = C5v to 5v, ltc2053i, ltc2053i-sync a v = 1, v cm = C4.9v to 4.9v, ltc2053h a v = 1, v cm = C5v to 5v, ltc2053h l l l l l l l 105 100 105 100 95 100 90 118 118 118 118 118 db db db db db db db power supply rejection ratio (note 6) v s = 2.7v to 11v l 110 116 db maximum output voltage swing r l = 2k to gnd, c- and i-grades r l = 10k to gnd, all grades r l = 2k to gnd, ltc2053h only l l l 4.5 4.6 4.4 4.8 4.9 4.8 v v v supply current no load l 0.95 1.3 ma supply current, shutdown v en 4.5v, ltc2053 only 20 a en pin input low voltage, v il C4.5 v clk pin input low voltage, v il 0.5 v en /clk pin input high voltage, v ih 4.5 v en /clk pin input current v en /clk = v C C3 C20 a internal op amp gain bandwidth 200 khz slew rate 0.2 v/s internal sampling frequency 3 khz the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v + = 5v, v C = C5v, ref = 0v.
ltc2053/ltc2053-sync 2053syncfc input common mode voltage (v) 0 input offset voltage ( v) 15 10 5 0 ?5 ?10 ?15 0.5 1.0 1.5 2.0 2053 g01 2.5 3.0 v s = 3v v ref = 0v t a = 25c g = 1000 g = 100 g = 10 g = 1 input common mode voltage (v) 0 input offset voltage (v) 15 10 5 0 ?5 ?10 ?15 1 2 3 4 2053 g02 5 v s = 5v v ref = 0v t a = 25c g = 1000 g = 100 g = 10 g = 1 input common mode voltage (v) ?5 input offset voltage ( v) 20 15 10 5 0 ?5 ?10 ?15 ?20 ?3 ?1 1 3 2053 g03 5 v s = 5v v ref = 0v t a = 25c g = 1000 g = 10 g = 1 g = 100 input common mode voltage (v) input offset voltage ( v) 20 15 10 5 0 ?5 ?10 ?15 ?20 2053 g04 0 0.5 1.0 1.5 2.0 2.5 3.0 v s = 3v v ref = 0v g = 10 t a = 25c t a = 85c t a = 70c t a = ?55c input common mode voltage (v) 0 input offset voltage ( v) 20 15 10 5 0 ?5 ?10 ?15 ?20 1 2 3 4 2053 g05 5 v s = 5v v ref = 0v g = 10 t a = 25c t a = 85c t a = ?55c t a = 70c input common mode voltage (v) ?5 input offset voltage ( v) 20 15 10 5 0 ?5 ?10 ?15 ?20 ?3 ?1 1 3 2053 g06 5 v s = 5v v ref = 0v g = 10 t a = 25c t a = 85c t a = ?55c t a = 70c note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: these parameters are guaranteed by design. thermocouple effects preclude measurement of these voltage levels in high speed automatic test systems. v os is measured to a limit determined by test equipment capability. note 3: if the total source resistance is less than 10k, no dc errors result from the input bias currents or the mismatch of the input bias currents or the mismatch of the resistances connected to Cin and +in. e lec t rical c harac t eris t ics note 4: the cmrr with a voltage gain, a v , larger than 10 is 120db (typ). note 5: at temperatures above 70c, the common mode rejection ratio lowers when the common mode input voltage is within 100mv of the supply rails. note 6: the power supply rejection ratio (psrr) measurement accuracy depends on the proximity of the power supply bypass capacitor to the device under test. because of this, the psrr is 100% tested to relaxed limits at final test. however, their values are guaranteed by design to meet the data sheet limits. input offset voltage vs input common mode voltage input offset voltage vs input common mode voltage typical p er f or m ance c harac t eris t ics input offset voltage vs input common mode voltage input offset voltage vs input common mode voltage input offset voltage vs input common mode voltage input offset voltage vs input common mode voltage
ltc2053/ltc2053-sync 2053syncfc input common mode voltage (v) input offset voltage ( v) 60 40 20 0 ?20 ?40 ?60 2053 g07 0 0.5 1.0 1.5 2.0 2.5 3.0 h-grade parts v s = 3v v ref = 0v g = 10 t a = 25c t a = 85c t a = 125c input common mode voltage (v) 0 input offset voltage ( v) 60 40 20 0 ?20 ?40 ?60 2053 g08 0 1 2 3 4 5 h-grade parts v s = 5v v ref = 0v g = 10 t a = 25c t a = 85c t a = 125c input common mode voltage (v) ?5 input offset voltage ( v) ?3 ?1 1 3 2053 g09 5 100 80 60 40 20 0 ?20 ?40 ?60 ?80 ?100 h-grade parts v s = 5v v ref = 0v g = 10 t a = 25c t a = 85c t a = 125c input common mode voltage (v) 0 additional offset error ( v) 60 40 20 0 ?20 ?40 ?60 0.5 1.0 1.5 2.0 2053 g10 2.5 3.0 v s = 3v v ref = 0v r + = r ? = r s c in < 100pf g = 10 t a = 25c r s = 0k r s = 20k r s = 10k r s = 5k + ? r s r s small c in r s = 15k input common mode voltage (v) 0 additional offset error (v) 30 20 10 0 ?10 ?20 ?30 1 2 3 4 2053 g11 5 v s = 5v v ref = 0v r + = r ? = r s c in < 100pf g = 10 t a = 25c r s = 20k r s = 15k r s = 10k r s = 5k ?5 ?3 ?1 1 3 5 input common mode voltage (v) additional offset error (v) 2053 g12 25 20 15 10 5 0 ?5 ?10 ?15 ?20 ?25 v s = 5v v ref = 0v r + = r ? = r s c in < 100pf g = 10 t a = 25c r s = 20k r s = 15k r s = 10k input common mode voltage (v) 0 additional offset error ( v) 0.5 1.0 1.5 2.0 2053 g13 2.5 3.0 50 40 30 20 10 0 ?10 ?20 ?30 ?40 ?50 v s = 3v v ref = 0v c in < 100pf g = 10 t a = 25c r + = 0k, r ? = 10k r + = 0k, r ? = 15k r + = 0k, r ? = 5k + ? r + r ? small c in r + = 15k, r ? = 0k r + = 5k, r ? = 0k r + = 10k, r ? = 0k input common mode voltage (v) 0 additional offset error (v) 1 2 3 4 2053 g14 5 40 30 20 10 0 ?10 ?20 ?30 ?40 v s = 5v v ref = 0v c in < 100pf g = 10 t a = 25c r in + = 0k, r in ? = 20k r in + = 0k, r in ? = 15k r in + = 0k, r in ? = 10k r in + = 15k, r in ? = 0k r in + = 10k, r in ? = 0k r in + = 20k, r in ? = 0k input common mode voltage (v) additional offset error (v) 2053 g15 40 30 20 10 0 ?10 ?20 ?30 ?40 v s = 5v v ref = 0v c in < 100pf g = 10 t a = 25c r + = 0k, r ? = 15k r + = 0k, r ? = 20k r + = 15k, r ? = 0k r + = 20k, r ? = 0k ?5 ?3 ?1 1 3 5 typical p er f or m ance c harac t eris t ics error due to input r s vs input common mode (c in < 100pf) error due to input r s vs input common mode (c in < 100pf) error due to input r s vs input common mode (c in < 100pf) error due to input r s mismatch vs input common mode (c in < 100pf) error due to input r s mismatch vs input common mode (c in < 100pf) error due to input r s mismatch vs input common mode (c in < 100pf) input offset voltage vs input common mode voltage input offset voltage vs input common mode voltage input offset voltage vs input common mode voltage
ltc2053/ltc2053-sync 2053syncfc input common mode voltage (v) 0 additional offset error (v) 0.5 1.0 1.5 2.0 2053 g16 2.5 3.0 40 30 20 10 0 ?10 ?20 ?30 ?40 v s = 3v v ref = 0v r + = r ? = r s c in > 1f g = 10 t a = 25c r s = 15k r s = 10k r s = 5k + ? r s r s big c in input common mode voltage (v) 0 additional offset error (v) 70 50 30 10 ?10 ?30 ?50 ?70 1 2 3 4 2053 g17 5 v s = 5v v ref = 0v r + = r ? = r s c in > 1f g = 10 t a = 25c r s = 500 r s = 10k r s = 1k r s = 5k input common mode voltage (v) additional offset error (v) 2053 g18 80 60 40 20 0 ?20 ?40 ?60 ?80 v s = 5v v ref = 0v r + = r ? = r s c in > 1f g = 10 t a = 25c ?5 ?3 ?1 1 3 5 r s = 500 r s = 10k r s = 1k r s = 5k input common mode voltage (v) additional offset error (v) 2053 g19 200 150 100 50 0 ?50 ?100 ?150 ?200 0 0.5 1.0 1.5 2.0 2.5 3.0 v s = 3v v ref = 0v t a = 25c + ? r + r ? big c in r + = 0k, r ? = 1k r + = 1k, r ? = 0k r + = 0k, r ? = 500 r + = 0k, r ? = 100 r + = 500, r ? = 0k r + = 100, r ? = 0k input common mode voltage (v) additional offset error (v) 2053 g20 200 150 100 50 0 50 ?100 ?150 ?200 0 0 1 2 3 4 5 v s = 5v v ref = 0v t a = 25c r + = 0k, r ? = 1k r + = 1k, r ? = 0k r + = 0k, r ? = 500 r + = 0k, r ? = 100 r + = 500, r ? = 0k r + = 100, r ? = 0k ?5 ?3 ?1 1 3 5 input common mode voltage (v) 2053 g21 additional offset error (v) 150 100 50 0 ?50 ?100 ?150 v s = 5v v ref = 0v t a = 25c r + = 0k, r ? = 1k r + = 1k, r ? = 0k r + = 0k, r ? = 100 r + = 0k, r ? = 500 r + = 100, r ? = 0k r + = 500, r ? = 0k ?50 input offset voltage (v) 80 60 40 20 0 ?20 ?40 ?60 ?80 temperature (c) 100 2053 g22 0 50 ?25 25 75 125 v s = 3v v s = 5v v s = 5v v ref (v) 0 v os (v) 30 20 10 0 ?10 ?20 ?30 2053 g23 1 2 3 4 v s = 3v v s = 5v v in + = v in ? = ref g = 10 t a = 25c 0 2 4 5 9 1 3 6 7 8 v ref (v) v os (v) 60 40 20 0 ?20 ?40 ?60 2053 g24 v s = 10v v in + = v in ? = ref g = 10 t a = 25c typical p er f or m ance c harac t eris t ics error due to input r s mismatch vs input common mode (c in >1f) error due to input r s mismatch vs input common mode (c in >1f) error due to input r s mismatch vs input common mode (c in >1f) offset voltage vs temperature v os vs ref (pin 5) v os vs ref (pin 5) error due to input r s vs input common mode (c in > 1f) error due to input r s vs input common mode (c in > 1f) error due to input r s vs input common mode (c in > 1f)
ltc2053/ltc2053-sync 2053syncfc output voltage (v) ?2.4 nonlinearity (ppm) 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 ?1.4 ?0.4 0.1 2053 g25 ?1.9 ?0.9 0.6 1.1 1.6 v s = 2.5v v ref = 0v g = 1 r l = 10k t a = 25c output voltage (v) ?2.4 nonlinearity (ppm) 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 ?1.4 ?0.4 2053 g26 0.6 1.6 2.6 v s = 2.5v v ref = 0v g = 10 r l = 10k t a = 25c frequency (hz) 1 cmrr (db) 130 120 110 100 90 80 70 10 100 1000 2053 g27 v s = 3v, 5v, 5v v in = 1v p-p r + = r ? = 1k r + = r ? = 10k r + = 10k, r ? = 0k + ? r + r ? r + = 0k, r ? = 10k frequency (hz) 1 input referred noise density (nv/ ? hz) 300 250 200 150 100 50 0 10 100 1000 10000 2053 g28 g = 10 t a = 25c v s = 5v v s = 5v v s = 3v time (s) 0 input referred noise voltage (v) 3 2 1 0 ?1 ?2 ?3 2 4 6 8 2053 g29 10 v s = 3v t a = 25c time (s) 0 input referred noise voltage (v) 3 2 1 0 ?1 ?2 ?3 2 4 6 8 2053 g30 10 v s = 5v t a = 25c output current (ma) 0.01 output voltage swing (v) 0.1 1 10 2053 g31 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 t a = 25c v s = 5v, sourcing v s = 3v, sourcing v s = 5v, sinking v s = 3v, sinking sourcing sinking output current (ma) 0.01 output voltage swing (v) 0.1 1 10 2053 g32 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 v s = 5v t a = 25c typical p er f or m ance c harac t eris t ics i v n d f i r n h b i r n h b o v s o c o v s o c g n g g n g cmrr f
ltc2053/ltc2053-sync 2053syncfc supply voltage (v) 2.5 supply current 10.5 2053 g33 4.5 6.5 8.5 1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 t a = ?55c t a = 85c t a = 125c t a = 0c settling accuracy (%) 0.0001 settling time (ms) 2053 g34 0.001 0.01 0.1 8 7 6 5 4 3 2 1 0 v s = 5v dv out = 1v g < 100 t a = 25c gain (v/v) 1 settling time (ms) 35 30 25 20 15 10 5 0 10 100 1000 10000 2053 g35 v s = 5v dv out = 1v 0.1% accuracy t a = 25c supply voltage (v) 2.5 clock frequency (khz) 10.5 2053 g36 4.5 6.5 8.5 3.40 3.35 3.30 3.25 3.20 3.15 3.10 t a = ?55c t a = 85c t a = 125c t a = 25c p in func t ions en (pin 1, ltc2053 only): active low enable pin. clk (pin 1, ltc2053-sync only): clock input for syn - chronizing to external system clock. Cin (pin 2): inverting input. +in (pin 3): noninverting input. v C (pin 4): negative supply. ref (pin 5): voltage reference (v ref ) for amplifier output. rg (pin 6): inverting input of internal op amp. see figure 1. out (pin 7): amplifier output. see figure 1. v + (pin 8): positive supply. typical p er f or m ance c harac t eris t ics settling time vs gain internal clock frequency vs supply voltage supply current vs supply voltage low gain settling time vs settling accuracy
ltc2053/ltc2053-sync 0 2053syncfc b lock diagra m ? + zero-drift op amp c h out 2053 bd 4 v ? 5 ref 6 rg 8 v + 1 en /clk* 3 +in 2 ?in c s 7 *note: pin 1 is en on the ltc2053 and clk on the ltc2053-sync a pplica t ions i n f or m a t ion theory of operation the ltc2053 uses an internal capacitor (c s ) to sample a differential input signal riding on a dc common mode voltage (see the block diagram). this capacitors charge is transferred to a second internal hold capacitor (c h ) trans - lating the common mode of the input differential signal to that of the ref pin. the resulting signal is amplified by a zero-drift op amp in the noninverting configuration. the rg pin is the negative input of this op amp and allows external programmability of the dc gain. simple filtering can be realized by using an external capacitor across the feedback resistor. input voltage range the input common mode voltage range of the ltc2053 is rail-to-rail. however, the following equation limits the size of the differential input voltage: v C (v + in C v C in ) + v ref v + C 1.3 where v + in and v C in are the voltages of the +in and Cin pins, respectively, v ref is the voltage at the ref pin and v + is the positive supply voltage. for example, with a 3v single supply and a 0v to 100mv differential input voltage, v ref must be between 0v and 1.6v. 5 volt operation when using the ltc2053 with supplies over 5.5v, care must be taken to limit the maximum difference between any of the input pins (+in or Cin) and the ref pin to 5.5v; if not, the device will be damaged. for example, if rail-to-rail input operation is desired when the supplies are at 5v, the ref pin should be 0v, 0.5v. as a second example, if v + is 10v and v C and ref are at 0v, the inputs should not exceed 5.5v. settling time the sampling rate is 3khz and the input sampling period during which c s is charged to the input differential voltage v in is approximately 150s. first assume that on each input sampling period, c s is charged fully to v in . since c s = c h (= 1000pf), a change in the input will settle to n bits of accuracy at the op amp noninverting input after n clock cycles or 333s(n). the settling time at the out pin is also affected by the settling of the internal op amp. since the gain bandwidth of the internal op amp is typically 200khz, the settling time is dominated by the switched capacitor front end for gains below 100 (see the typical performance characteristics section).
ltc2053/ltc2053-sync 2053syncfc input current whenever the differential input v in changes, c h must be c harged up to the new input voltage via c s . this results in an input charging current during each input sampling period. eventually, c h and c s will reach v in and, ideally, the input current would go to zero for dc inputs. in reality, there are additional parasitic capacitors which disturb the charge on c s every cycle even if v in is a dc voltage. for example, the parasitic bottom plate capacitor on c s must be charged from the voltage on the ref pin to the voltage on the Cin pin every cycle. the resulting input charging current decays exponentially during each input sampling period with a time constant equal to r s c s . if the voltage disturbance due to these currents settles before the end of the sampling period, there will be no errors due to source resistance or the source resistance mismatch between Cin and +in. with r s less than 10k, no dc errors occur due to this input current. in the typical performance characteristics section of this data sheet, there are curves showing the additional error from non-zero source resistance in the inputs. if there are no large capacitors across the inputs, the amplifier is less sensitive to source resistance and source resistance mismatch. when large capacitors are placed across the inputs, the input charging currents previously described result in larger dc errors, especially with source resistor mismatches. power supply bypassing the ltc2053 uses a sampled data technique and, therefore, contain s some clocked digital circuitry. it is, therefore, sensitive to supply bypassing. for single or dual supply operation, a 0.1f ceramic capacitor must be connected between pin 8 ( v + ) and pin 4 ( v C ) with leads as short as possible. synchronizing to an external clock (ltc2053-sync only) the ltc2053 has an internally generated sample clock that is typically 3khz. there is no need to provide the ltc2053 with a clock. however, in some applications, it may be desirable for the user to control the sampling frequency more precisely to avoid undesirable aliasing. this can be done with the ltc2053-sync. this device uses pin 1 as a clock input whereas the ltc2053 uses pin 1 as an enable pin. if clk (pin 1) is left floating on the ltc2053-sync, the device will run on its internal oscillator, similar to the ltc2053. however, if not externally synchronizing to a system clock, it is recommended that the ltc2053 be used instead of the ltc2053-sync because the ltc2053- sync is sensitive to parasitic capacitance on the clk pin when left floating. clocking the ltc2053-sync is accom- plished by driving the clk pin at 8 times the desired sample clock frequency. this completely disables the internal clock. for example, to achieve the nominal ltc2053 sample clock rate of 3khz, a 24khz external clock should be applied to the clk pin of the ltc2053 -sync. a pplica t ions i n f or m a t ion ? + ? + v in v +in v out v ?in 3 8 5v 4 5 6 7 2 ? + ? + v in v +in v out v ?in v ref v ref v ref ?5v 3 8 5v 5v ?5v < v ?in < 5v and | v ?in ? v ref | < 5.5v ?5v < v +in < 5v and | v +in ? v ref | < 5.5v ?5v < v in + v ref < 3.7v single supply, unity gain ? + ? + v in v +in v out v ?in 3 8 5v 4 5 6 7 2 0v < v +in < 5v 0v < v ?in < 5v 0v < v in < 3.7v v out = v in single supply, unity gain dual supply, nonunity gain 4 5 6 r2 r1 7 2 v out = 1 + v in + v ref r2 r1 0v < v ?in < 5v and | v ?in ? v ref | < 5.5v 0v < v +in < 5v and | v +in ? v ref | < 5.5v 0v < v in + v ref < 3.7v v out = v in + v ref ? + ? + v in v +in v out v ?in ?5v 3 2053 f01 8 ?5v < v ?in < 5v and | v ?in ? v ref | < 5.5v ?5v < v +in < 5v and | v +in ? v ref | < 5.5v ?5v < v in + v ref < 3.7v dual supply, nonunity gain 4 5 6 r2 r1 7 2 v out = 1 + (v in + v ref ) r2 r1 figure 1
ltc2053/ltc2053-sync 2053syncfc a pplica t ions i n f or m a t ion figure 2. centered justified for a single line of text if a square wave is used to drive the clk pin, a 5s rc time constant should be placed in front of the clk pin to maintain low offset voltage performance (see figure 2). this avoids internal and external coupling of the high frequency components of the external clock at the instant the ltc2053-sync holds the sampled input. ? + ? + v d v +in v out external clock v ?in 3 2053 f02 8 5v 4 5 1 6 r2 1k r1 7 2 ltc2053-sync clk 5v 4.7nf 0v the ltc2053-sync is tested with a sample clock of 3khz (f clk = 24khz) to the same specifications as the ltc2053. in addition, the ltc2053-sync is tested at one-half and 2x this frequency to verify proper operation. the curves in the typical performance characteristics section of this data sheet apply to the ltc2053-sync when driving it with a 24khz clock at pin 1 (f clk = 24khz, 3khz sample clock rate). below are three curves that show the behavior of the ltc2053-sync as the clock frequency is varied. the offset is essentially unaffected over a 2:1 increase or decrease of the typical ltc2053 sample clock speed. the bias current is directly proportional to the clock speed. the noise is roughly proportional to the square root of the clock frequency. for optimum noise and bias current performance, drive the ltc2053-sync with a nominal 24khz external clock (3khz sample clock). figure 3. ltc2053-sync input offset vs sample frequency sample frequency (hz) (= f clk /8) 0 input offset ( v) 20 15 10 5 0 ?5 ?10 ?15 ?20 2000 4000 6000 8000 2053 f03 10000 v s = 5v v s = 5v v s = 3v typ ltc2053 sample frequency sample frequency (hz) (= f clk /8) 0 input bias current (na) 14 12 10 8 6 4 2 0 2000 4000 6000 8000 2053 f04 10000 v s = 5v v ref = 0 v cm = 1v typ ltc2053 sample frequency sample frequency (f clk /8) 0 input referred noise voltage (v pp ) 12 10 8 6 4 2 0 2000 4000 6000 8000 2053 f05 10000 typ ltc2053 sample frequency v s = 5v t a = 25c noise in 10hz bandwidth figure 4. ltc2053-sync average input bias current vs sample frequency figure 5. ltc2053-sync input referred noise vs sample frequency
ltc2053/ltc2053-sync 2053syncfc typical a pplica t ions precision current source precision 2 (low noise 2.5v reference) precision doubler (general purpose) precision inversion (general purpose) v out v c 2053 ta02 1 4 5 6 7 5v 8 3 2 0.1f 0.1f 2.7k 10k r i load v c r i = ? , i 5ma 0 < v out < (5v ? v c ) ? + ltc2053 ref en rg 2053 ta03 ? + 1 1 4 4 5 6 7 8v ltc2053 8 8 3 2 2 0.1f 1f 0.1f 1k 2.5v (110nv/ ? hz) lt1027 ? 5 2053 ta04 ? + 1 4 5 6 7 5v ltc2053 8 3 2 0.1 m f 0.1f 0.1f ?5v v in v out v out = 2 v in v in 2053 ta05 ? + 1 4 5 6 7 5v ltc2053 8 3 2 0.1f 0.1f ?5v v out v out = ? v in
ltc2053/ltc2053-sync 2053syncfc typical a pplica t ions differential thermocouple amplifier high side power supply current sense ? + ltc2053 load v reg 0.0015 7 i load 0.1 f 0.1 f 10k 150 2 3 1, 4 5 6 7 8 out 100mv/a of load current 2053 ta07 2053 ta06 ? + ? ? + + 5v 5v 5v 100 scale factor trim 10mv/c 249k 1% 1k 1% 1 2 3 4 5 6 7 8 0.1 f 0.001 f 0.001 f 0.1 f 10k 10k 1m 1m 10m 10m en yellow orange 0c m 500c type k thermocouple (40.6v/c) lt1025 v o r ? 2 3 3 4 6 1 2 4 5 200k ltc2053 ref rg thermal coupling 0.1 f ltc2050
ltc2053/ltc2053-sync 2053syncfc 3.00 p 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.40 p 0.10 bottom view?exposed pad 1.65 p 0.10 (2 sides) 0.75 p 0.05 r = 0.125 typ 2.38 p 0.10 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 ? 0.05 (dd8) dfn 0509 rev c 0.25 p 0.05 2.38 p 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 p 0.05 (2 sides) 2.10 p 0.05 0.50 bsc 0.70 p 0.05 3.5 p 0.05 package outline 0.25 p 0.05 0.50 bsc dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698 rev c) p ackage descrip t ion
ltc2053/ltc2053-sync 2053syncfc p ackage descrip t ion msop (ms8) 0307 rev f 0.53 p 0.152 (.021 p .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.1016 p 0.0508 (.004 p .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 o ? 6 o typ detail ?a? detail ?a? gauge plane 1 2 3 4 4.90 p 0.152 (.193 p .006) 8 7 6 5 3.00 p 0.102 (.118 p .004) (note 3) 3.00 p 0.102 (.118 p .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.42 p 0.038 (.0165 p .0015) typ 0.65 (.0256) bsc ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f)
ltc2053/ltc2053-sync 2053syncfc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory (revision history begins at rev c) rev date description page number c 7/10 corrected text in the absolute maximum ratings section 2 updated pin 6 and pin 7 text in the pin functions section 9 replaced figure 1 11
ltc2053/ltc2053-sync 2053syncfc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0710 rev c ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments lt1167 single resistor gain-programmable, precision instrumentation amplifier single-gain set resistor: g = 1 to 10,000, low noise: 7.5nv hz ltc2050/ltc2051 zero-drift single/dual operation amplifier sot-23 and ms8 packages ltc2054/ltc2055 zero-drift power operational amplifier sot-23 and ms8 packages, 150a/op amp ltc6800 single-supply, zero-drift, rail-to-rail input and output instrumentation amplifier ms8 package, 100v max v os , 250nv/c max drift linearized platinum rtd amplifier ? + 1 4 5 6 7 ltc2053 8 3 2 0.1f 2.7k 1.21k 5v 5v ? + 1 4 5 6 7 ltc2053 8 3 2 5v 0.1f pt100* 3-wire rtd 0.1f 0.1f 0.1f 1m 16.2k 16.9k 10k 24.9k 11k cw cw cw 39.2k 5k gain linearity 10k 49.9 249k lt1634-1.25 zero 100 953 10mv/c 0c ? 400c (0.1c) 2053 ta08 i 1ma *conforming to iec751 or din43760 r t = r o (1 + 3.908 ? 10 ?3 t ? 5.775 ? 10 ?7 t 2 ), r o = 100 (e.g., 100 at 0c, 175.9 at 200c, 247.1 at 400c)

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